Stacked Switched Capacitor Energy Buffer Circuit

ABSTRACT

A stacked switched capacitor (SSC) energy buffer circuit includes a switching network and a plurality of energy storage capacitors. The switching network need operate at only a relatively low switching frequency and can take advantage of soft charging of the energy storage capacitors to reduce loss. Thus, efficiency of the SSC energy buffer circuit can be extremely high compared with the efficiency of other energy buffer circuits. Since circuits utilizing the SSC energy buffer architecture need not utilize electrolytic capacitors, circuits utilizing the SSC energy buffer architecture overcome limitations of energy buffers utilizing electrolytic capacitors. Circuits utilizing the SSC energy buffer architecture (without electrolytic capacitors) can achieve an effective energy density characteristic comparable to energy buffers utilizing electrolytic capacitors. The SSC energy buffer architecture exhibits losses that scale with the amount of energy buffered, such that a relatively high efficiency can be achieved across a desired operating range.

BACKGROUND

As is known in the art, power conversion systems that interface betweendirect current (DC) and single-phase alternating current (AC) require anenergy storage capability (or an energy buffer) which provides bufferingbetween a constant power desired by a DC source or a load and acontinuously varying power desired for a single-phase AC system.

As is also known, the flow to and from such an energy buffer is at twicethe line frequency (e.g., 120 Hz in the United States). The bufferingenergy requirement can be calculated as E_(buf)=P/ω_(line). Because theenergy storage requirement of the buffer is proportional to the systemaverage power (P) and the (relatively long) line period (T=2π/ω), thesize of the required energy buffer cannot be reduced simply throughincreases in switching frequency of an interface power converter. Thus,energy buffering requirements represent a significant limitation onminiaturization of grid interface systems.

One important consideration associated with twice-line-frequency energybuffering relates to lifetime and reliability. Conventional powerconversion systems typically utilize electrolytic capacitors to providehigh-density energy storage for buffering. It is, however, widelyappreciated that despite providing the best available energy density andproviding small DC bus voltage variation, electrolytic capacitors alsorepresent a significant source of system lifetime and reliabilityproblems. Also, electrolytic capacitors can only be operated over anarrow charge/discharge range at 120 Hz for thermal and efficiencyreasons (i.e., associated with RMS current limits and efficiencyrequirements). These considerations directly limit the energy bufferingcapability of electrolytic capacitors at 120 Hz. Thus, while typicalpeak energy storage densities of up to 0.9 J/cm³ can be achieved withelectrolytic capacitors, the allowable energy swing at 120 Hz yieldspractical energy densities that are about an order of magnitude lower.Hence, the development of energy buffering circuits that eliminateelectrolytic capacitors while maintaining high energy storage densityand high efficiency is one important requirement to achieving futuregrid interface systems that have both a small size and a highreliability.

It is known that film capacitors have a reliability and lifetime whichis higher than electrolytic capacitors, but it is also known that filmcapacitors have considerably lower peak energy density than electrolyticcapacitors (by an order of magnitude).

However, because film capacitors can be efficiently charged anddischarged over a much wider voltage range compared withcharge/discharge voltage ranges of electrolytic capacitors, for 120 Hzbuffering, energy densities similar to those achieved with practicalsystems which utilize electrolytic capacitors can be achieved withhigh-reliability film capacitors, so long as a wide variation of thecapacitor voltage can be used.

One approach to develop energy buffering circuits that eliminateelectrolytic capacitors utilizes active filter blocks (essentiallybidirectional DC-DC converters). The active filter block approacheffectively utilizes film capacitors while maintaining a desirednarrow-range bus voltage. While this approach is flexible in terms of ituse, it unfortunately leads to low buffering efficiency if high powerdensity is to be maintained, due to losses in the active filter.

Other systems have incorporated the required energy buffering as part ofthe operation of the grid interface power stage. This approach canoffset a portion of the buffering loss associated with introduction of acomplete additional power conversion stage, but still introduceshigh-frequency loss and is quite restrictive in terms of operation andapplication.

As is also known in the prior art, energy buffering can be employed inmany non-line-frequency applications where there is a energy transferredbetween a first source or load having a slow rate of varying powerand/or a limited instantaneous power rating (perhaps a dc source orload) and a second source or load that has a component of power thatvaries faster and/or to an instantaneous value larger than that desiredto be sourced or absorbed by the first source or load. For example, suchapplications include interfacing a battery system (which is desired tobe efficiently charged or discharged at a limited rate and with alimited peak power) to a mechanical system that requires rapidly varyingpower flow and perhaps large peak power (e.g., by using a powerconverter driving an electromechanical system such as a motor). In sucha system, an energy buffer is desired to provide the local-timedifference between the power sourced or absorbed by the first source orload and the second source or load (e.g., the difference between thatdesired for the battery and that required by the power converter andmotor for the mechanical system). In such applications, an energy buffermay be provided by an ultracapacitor or energy buffer system includingone or more ultracapacitors. Applications requiring energy buffering ofthe nature described here may include, without limitation, motor drives,electric and hybrid vehicle drive trains, cranes, renewable energysystems including wind and wave energy systems, active filter andreactive power compensation systems, traction systems, laser driversystems, electromagnetic launch systems, electromagnetic guns,electromagnetic brakes and propulsion systems, and power systems forimplanted medical devices.

SUMMARY

In accordance with the concepts, systems, circuits and techniquesdescribed herein, a stacked switched capacitor (SSC) energy buffercircuit comprises a plurality of series-connected blocks of switches andcapacitors. The capacitors are preferably of a type that can beefficiently charged and discharged over a wide voltage range over abuffering time period of interest (e.g., film capacitors forline-frequency applications, and electrolytic capacitors orultracapacitors for mechanical system time scale applications). Thus,selection of the particular capacitor type and characteristics depends,at least in part, upon the particular application and the buffering timeperiod. In some embodiments, ultra-capacitors or electrolytic capacitorscould be used. The switches are disposed to selectively couple thecapacitors to enable dynamic reconfiguration of both the interconnectionamong the capacitors and their connection to a buffer port. The switchesare cooperatively operated as a switching network such that the voltageseen at the buffer port varies only over a small range as the capacitorscharge and discharge over a wide range to buffer energy.

With this particular arrangement, an energy buffer circuit having aneffective energy density which is relatively high compared with theeffective energy density of conventional energy buffer circuits isprovided. In some embodiments, efficiency can be extremely high becausethe switching network need operate at relatively low (e.g. line-scale)switching frequencies, and the system can take advantage of softcharging or adiabatic charging of the energy storage capacitors toreduce loss. Moreover, the stacked switched capacitor bufferarchitecture described herein exhibits losses that reduce as energybuffering requirements reduce such that high efficiency can be achievedacross an entire desired operating range.

In accordance with a further aspect of the concepts, systems, circuitsand techniques described herein a grid interface power convertercomprises an first filter having a first port adapted to receive aninput voltage from a DC source, a resonant high frequency isolated DC-DCconverter having a first port coupled to a second port of the firstfilter, a resonant high frequency inverter having a first port coupledto a second port of the resonant high frequency isolated DC-DC converterand having a second port coupled to a first port of a second filter withthe second filter having a second port adapted to receive an inputvoltage from a AC source. The grid interface power converter furthercomprises a stacked switched capacitor (SSC) energy buffer circuitcoupled between the second port of the resonant high frequency isolatedDC-DC converter and the first port of the resonant high frequencyinverter. By appropriately modifying switch states of the SSC energybuffer circuit, the SSC energy buffer circuit absorbs and deliversenergy over a wide individual capacitor voltage range, while maintaininga narrow-range voltage at the input port. This enables maximalutilization of the energy storage capability.

In accordance with a further aspect of the concepts, systems, circuitsand techniques described herein a grid interface power convertercomprises a DC-DC converter having a first port adapted to connect to aDC source or load, a DC-AC converter having a first port coupled to asecond port of the DC-DC converter and having a second port adapted toconnect to a AC source or load. The grid interface power converterfurther comprises a stacked switched capacitor (SSC) energy buffercircuit coupled between the second port of the DC-DC converter and thefirst port of the DC-AC converter. By appropriately modifying switchstates of the SSC energy buffer circuit, the SSC energy buffer circuitabsorbs and delivers energy over a wide individual capacitor voltagerange, while maintaining a narrow-range voltage at the input port. Thisenables relatively high utilization, and in some cases maximalutilization, of the energy storage capability.

With this particular arrangement, an energy buffering approachapplicable to a wide range of grid-interface power electronicapplications is provided. Grid-interface power electronic applicationsinclude but are not limited to photovoltaic inverters, motor drives,power supplies, off-line LED drivers and plug-in hybrid electric vehiclechargers. Use of the energy buffering approach described herein resultsin improved reliability and lifetime in these and other applications.

In one embodiment, a stacked switched capacitor (SSC) energy buffercircuit includes a switching network comprised of a plurality ofswitches and a plurality of energy storage capacitors which may beprovided as film capacitors. Switches in the switching network areconfigured to selectively couple at least one of the energy storagecapacitors in series across a bus voltage. The switching network needoperate at only a relatively low switching frequency, and the system cantake advantage of soft charging of the energy storage capacitors toreduce loss. Thus, efficiency of the SSC energy buffer circuit can beextremely high compared with the efficiency of other energy buffercircuits. Furthermore, since circuits utilizing the SSC energy bufferarchitecture need not utilize electrolytic capacitors, circuitsutilizing the SSC energy buffer architecture overcome limitations ofenergy buffers which do utilize electrolytic capacitors. Furthermore,circuits utilizing the SSC energy buffer architecture (but not usingutilizing electrolytic capacitors) can achieve an effective energydensity characteristic comparable to energy buffers which utilizeelectrolytic capacitors. In some cases, circuits using the SSC energybuffer architecture, either with or without electrolytic capacitors, canachieve higher effective energy than a circuit using electrolyticcapacitors alone for the same voltage ripple. Moreover, the SSC energybuffer architecture exhibits losses that scale with the amount of energythat must be buffered, such that a relatively high efficiency can beachieved across a desired operating range.

In accordance with a further aspect of the concepts, systems, circuitsand techniques described herein, a stacked switched capacitor (SSC)energy buffer circuit having first and second terminals includes a firstsub-circuit comprising one or more capacitors, a second sub-circuitcomprising one or more capacitors and one or more switches disposed inat least one of said first and second sub-circuits. The one or moreswitches are cooperatively operated to selectively couple the one ormore capacitors within and/or between the first and second sub-circuits.In a first operating mode, the first and second sub-circuits areserially coupled and the one or more switches are operable to enabledynamic reconfiguration of how the capacitors are coupled to theterminals of the sub-circuit.

In one embodiment, the one or more switches are operable to dynamicallyreconfigure the interconnection among the capacitors within at least oneof said first and second sub-circuits.

In one embodiment, in at least some operating modes of the SSC energybuffer circuit, the one or more switches are operable to prevent thecapacitors from ever being connected together at both terminals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is circuit diagram of a parallel-series switched capacitorcircuit.

FIGS. 1 and 1C are circuit diagrams of two configurations associatedwith FIG. 1A for different switch states.

FIG. 2 is a circuit diagram of a stacked switched capacitor (SSC) energybuffer circuit.

FIG. 3 is a block diagram of a grid interface power converter systemusing the SSC energy buffer circuit of FIG. 2.

FIG. 3A is a block diagram of a general grid interface power convertersystem using the SSC energy buffer circuit of FIG. 2.

FIG. 4 is a circuit diagram of an example of the SSC energy buffercircuit called a 2-4 bipolar SSC energy buffer circuit.

FIG. 5 is a plot of switch states vs. voltages of the circuit in FIG. 4.

FIG. 6 is a circuit diagram of another example of the SSC energy buffercircuit called a 1-3 unipolar SSC energy buffer circuit.

FIG. 7 is a plot of switch states vs. voltages of the circuit in FIG. 6.

FIG. 8 is a plot of switch states vs. voltages of the circuit in FIG. 6using a modified control.

FIG. 9 is a circuit diagram of a generalized example of the SSC energybuffer circuit of FIG. 6 called a 1-m unipolar SSC energy buffercircuit.

FIG. 10 is a circuit diagram of an example of the SSC energy buffercircuit of FIG. 2 called a 1-3 bipolar SSC energy buffer circuit.

FIG. 11 is a plot of switch states vs. voltages of the circuit in FIG.10.

FIG. 12 is a circuit diagram of an example of the SSC energy buffercircuit of FIG. 2 called an n-m bipolar SSC energy buffer circuit.

FIG. 13 is a plot of energy buffering ratio versus a number of mcapacitors with a voltage ripple ratio of 12.5% for different numbers ofn capacitors.

FIG. 14A is a plot of energy buffering ratio versus a number of mcapacitors with a voltage ripple ratio of 25% for different numbers of ncapacitors.

FIG. 14B is a plot of energy buffering ratio versus a number of mcapacitors with a voltage ripple ratio of 6.25% for different numbers ofn capacitors.

FIG. 15 is a circuit diagram of another example of the SSC energy buffercircuit called a 2-6 bipolar SSC energy buffer circuit.

FIG. 16 is a plot of switch states vs. voltages of the circuit in FIG.15.

FIG. 17 is a plot of energy buffering ratio versus and the number of mcapacitors for different numbers of n capacitors and whether undermodified control.

DETAILED DESCRIPTION

Described herein is a switched capacitor structure referred to herein asstacked switched capacitor (SSC) energy buffer circuit. Althoughreference is sometimes made herein to use of an energy buffer circuit ina particular application, it should be appreciated that the energybuffer circuits, concepts and techniques described herein find use in awide variety of applications. For example, many applications exist inwhich an energy buffer is used because either a peak power rating or adesired energy transfer rating of a first source or load is differentfrom that of the source or load to which it interfaces. It should berecognized that the concepts, systems, circuits and techniques describedherein can be used in these applications to achieve one or more of:higher energy density/smaller size at a given voltage variation level,higher reliability by using more desirable energy storage elements.

The SSC energy buffer circuit provides a small variation of a busvoltage, V_(bus) while also providing high utilization of available peakenergy storage capacity. In one embodiment, a variation of 12.5% or lessis provided while providing utilization of available peak energy storagecapacity of 72.7% or better. The SSC energy buffer circuit and relatedtechniques described herein achieves extremely high efficiency (e.g., byusing film capacitors) and uses simpler circuitry. The SSC energy buffercircuit and related techniques described herein achieves extremely highenergy density e.g., by incorporating film capacitors, electrolyticcapacitors or ultracapacitors and employing them over a wider voltagerange than appears at the input port. The SSC energy buffer circuit andrelated techniques described herein provide performance characteristicscomparable to or better than conventional energy buffer circuits whileat the same time utilizing fewer switches and capacitors thanconventional energy buffer circuits. The SSC energy buffer circuitincludes a number of variations as will be described herein.

Referring to FIGS. 1A to 1C, switched capacitor circuits thatreconfigure capacitors between parallel and series combinations havebeen used to improve the energy utilization of ultracapacitors. Acircuit 10 is a simple version of a parallel-series switched capacitorcircuit. The circuit 10 includes switches S₁, S₂, S₃ and two capacitorsC₁ and C₂. The circuit 10 also includes a terminal 12 and a terminal 14(collectively referred to herein as a buffer port) to provide a busvoltage, V_(bus), cross the terminals 12, 14. When switches S₁ and S₃are open and S₂ is closed, the resulting configuration is represented bya circuit 10′ as shown in FIG. 1B depicting capacitors C₁ and C₂ inseries. When switches S₁ and S₃ are closed and S₂ is open, the resultingconfiguration is represented by a circuit 10″ shown in FIG. 1C depictingcapacitors C₁ and C₂ in parallel.

While the circuit 10 has a high capacitor energy utilization of 93.75%which is relatively high compared with prior art approaches, the circuit10 also has a voltage ripple ratio of 33.3% which is also relativelyhigh compared with prior art approaches. That is, the value of the busvoltage, V_(bus), varies by as much as 33.3%. For example, in oneembodiment, the voltage of the dc bus varies from 0.67V_(nom) to1.33V_(nom) where V_(nom) is the average (nominal) value of the busvoltage. More complex parallel-series switched capacitor circuits havealso been developed which achieve a better voltage ripple ratio;however, these complex parallel-series switched capacitors have highcircuit complexity when high energy utilization and small voltage rippleare required. For example, a circuit currently having among the bestperformance (e.g., a 8-6-5-4-3 parallel-series switched capacitorcircuit) has an energy utilization of 92.09% and a voltage ripple ratioof 14.3%, but requires 41 switches and 120 capacitors making the circuitrelatively complicated and thus relatively difficult to implement foruse in practical circuits and systems.

Referring to FIG. 2, a stacked switched capacitor (SSC) energy buffercircuit 100 overcomes the deficiencies of the switched capacitorcircuits like that of the circuit 10 (FIG. 1). The SSC energy buffercircuit 100 includes a first set of circuitry 102 and a second set ofcircuitry 104 connected in series. SSC energy buffer circuit 100 furtherincludes a pre-charge circuit 105. For reasons which will becomeapparent from the description provided herein below, pre-charge circuit105 is coupled to each of the two sub-circuits 102, 104 and pre-chargecircuit 105 is operable to charge each of one or more capacitors in twosub-circuits 102, 104 to specified initial conditions before entering afirst operating mode. In some cases, the pre-charge circuit 105 may becoupled in series with each of the two sub-circuits 102, 104 beforeentering a first operating mode, and further connections of thepre-charge circuit 105 to capacitors within the two sub-circuits 102,104 may be made with switches in the two sub-circuits 102, 104

The circuit 100 also includes a terminal 112, a terminal 113 and aterminal 114. Terminals 112, 114 collectively form a buffer port toprovide the bus voltage, V_(BUS). Each set of circuitry 102, 104includes capacitors.

As illustrated in FIG. 2, the first set of circuitry 102 includescapacitors C₁₁, C₁₂, . . . , C_(1n) and the second set of circuitry 104includes capacitors C₂₁, C₂₂, . . . , C_(2m) where n and m are integersgreater than or equal to one. The capacitors C₁₁, C₁₂, . . . , C_(1n),C₂₁, C₂₂, . . . , C_(2m), are of a type that can be efficiently chargedand discharged over a wide voltage range (e.g., film capacitorselectrolytic capacitors and ultra capacitors).

Each set of circuitry also includes switches. As illustrated in FIG. 2,the first set of circuitry 102 includes switches S₁₁, S₁₂, . . . ,S_(1n) and the second set of circuitry 104 includes switches S₂₁, S₂₂, .. . , S_(2m) connected in series with a respective one capacitor. Forexample, the switch S₁₁ is in series with the capacitor C₁₁, the switchS₁₂ is in series with the capacitor C₁₂, the switch S₂₁ is in serieswith the capacitor C₂₁, the switch S₂₂ is in series with the capacitorC₂₂ and so forth. The switches S₁₁, S₁₂, . . . , S_(1m) and S₂₁, S₂₂, .. . , S_(2n) enable dynamic reconfiguration of both the interconnectionamong the capacitors and their connection to the buffer port to providethe bus voltage, V_(bus).

It should, of course, be appreciated that in some implementations thereis no one-to-one correspondence between capacitors and switches, thatis, a “leg” can be just a capacitor as C₁₁ is in FIG. 6, just a switchas S₁₁ is in FIG. 6, or a switch in series with a capacitor as in manycases. Also one of the blocks can have switches not associated with a“leg” to allow the “legs” of that block to be connected in reverse, asS_(h1), S_(h2), S_(h3) and S_(h4) do in FIG. 4.

The switching in the circuit 100 (i.e., opening and closing of theswitches) is preferably performed such that the voltage seen at thebuffer port, V_(bus), varies only over a small range as the capacitorscharge and discharge over a wide voltage range to buffer energy, therebyproviding a high effective energy density. By appropriately modifyingthe switch states, the buffer capacitors absorb and deliver energy overa relatively wide individual voltage range, while maintaining arelatively narrow-range voltage at the input port. This enables a highdegree of utilization (and in some cases, even maximal utilization) ofthe capacitor energy storage capability. Efficiency of the circuit 100can be extremely high because the switches in the circuit 100 needoperate at only very low (line-scale) switching frequencies. Also, thecircuit 100 can take advantage of soft charging of the energy storagecapacitors to reduce loss. Moreover, the circuit 100 exhibits lossesthat reduce as energy buffering requirements reduce such that highefficiency can be achieved across the full operating range.

Referring to FIG. 3, the SSC energy buffer circuit 100 may be includedinto a grid interface power converter system 200. The system 200includes a DC power source 202 coupled to an input filter with parasiticcompensation 204, a resonant high frequency isolated DC-DC converter 206coupled to the SSC energy buffer circuit 100 through the terminals 112,114 that provide the bus voltage, V_(bus). The system 200 also includesan AC power source 212 coupled to an input filter with parasiticcompensation 214, a resonant high frequency inverter 216 coupled to theSSC energy buffer circuit 100 through the terminals 112, 114. Thisenergy buffering approach is applicable to a wide range ofgrid-interface power electronic applications (including photovoltaicinverters, motor drives, power supplies, off-line LED drivers andplug-in hybrid electric vehicle chargers and so forth), enablingimproved reliability and lifetime in these applications.

Referring to FIG. 3A, a grid interface power converter includes a DC-DCconverter having a first port adapted to connect to a DC source or load.The grid interface power converter further includes a DC-AC converterhaving a first port coupled to a second port of the DC-DC converter andhaving a second port adapted to connect to an AC source or load. Thegrid interface power converter further comprises a stacked switchedcapacitor (SSC) energy buffer circuit coupled between the second port ofthe DC-DC converter and the first port of the DC-AC converter. Byappropriately modifying switch states of the SSC energy buffer circuit,the SSC energy buffer circuit absorbs and delivers energy over a wideindividual capacitor voltage range, while maintaining a narrow-rangevoltage at the input port. This enables relatively high utilization, andin some cases maximal utilization, of the energy storage capability

Referring to FIG. 4, one particular example of the SSC energy buffercircuit 100 is a circuit 300 called a 2-4 bipolar SSC energy buffercircuit. The circuit 300 includes a first set of circuitry 302 and asecond set of circuitry 304 in series with the first set of circuitry302. The first set of circuitry 302 includes four “legs” each of whichcomprise four switches S₂₁, S₂₂, S₂₃, S₂₄ series coupled with respectiveones of four capacitors C₂₁, C₂₂, C₂₃, C₂₄ (e.g., the switch S₂₁ is inseries with the capacitor C₂₁, the switch S₂₂ is in series with thecapacitor C₂₂, the switch S₂₃ is in series with the capacitor C₂₃, andthe switch S₂₄ is in series with the capacitor C₂₄ and so forth). Thecapacitors C₂₁, C₂₂, C₂₃, C₂₄ can be in the circuit 300 in a positive ora negative manner (hence the term “bipolar”).

The first circuitry 302 also includes switches S₂, S_(h1), S_(h3),S_(h4) (sometimes referred herein collectively as an H-bridge) andselectively opening and closing the switches allows for bi-polarcharging. The second set of circuitry 304 includes two capacitors C₁₁,C₁₂ and two switches S₁₁, S₁₂ serially coupled to a respective one ofthe two capacitors C₁₁, C₁₂ (e.g., the switch S₁₁ is in series with thecapacitor C₁₁ and the switch S₁₂ is in series with the capacitor C₁₂).The circuit 300 also includes a terminal 312 and a terminal 314 thatcollectively form a buffer port to provide the bus voltage, V_(bus).

The capacitors C₁₁, C₁₂, C₂₁, C₂₂, C₂₃, C₂₄ have corresponding voltagesV₁₁, V₁₂, V₂₁, V₂₂, V₂₃, V₂₄ respectively. The capacitors C₁₁, C₁₂, C₂₁,C₂₂, C₂₃, C₂₄ have identical capacitance, but different voltage ratings.For example, the capacitors, C₁₁, C₁₂ each have a voltage rating of 13/8V_(nom), where V_(nom) is the nominal value of the bus voltage, V_(bus).The voltage rating of the capacitors C₂₁, C₂₂, C₂₃, C₂₄ are 5/8 V_(nom),4/8 V_(nom), 3/8 V_(nom), and 2/8 V_(nom), respectively. Pre-chargingcircuitry (not shown in FIG. 4) ensures that the following initialvoltages V₁₁, V₁₂, V₂₁, V₂₂, V₂₃, V₂₄ for the capacitors C₁₁, C₁₂, C₂₁,C₂₂, C₂₃, C₂₄ are 3/8 V_(nom), 3/8 V_(nom), 4/8 V_(nom), 3/8 V_(nom),2/8 V_(nom), and 1/8 V_(nom), respectively.

Referring to FIG. 5, when the circuit 300 begins charging from itsminimum state of charge, switches S_(h1), S_(h4), S₂₁, S₁₁ are turned onwhile switches S_(h2), S_(h3), S₁₂, S₂₂, S₂₃, S₂₄ are turned off. In theminimum state of charge, the capacitors C₁₁, C₂₁ are connected in seriesand charged until the bus voltage, V_(bus), rises from 7/8 V_(nom) to9/8 V_(nom). At this instant, the voltage, V₂₁, of the capacitor C₂₁reaches 5/8 V_(nom) and the voltage, V₁₁, of the capacitor C₁₁ reaches4/8 V_(nom).

Then, the switch S₂₁ is turned off, the switch S₂₂ is turned on; and thebus voltage, V_(bus), drops back down to 7/8 V_(nom). After a similarperiod of time (assuming a constant charging current) the voltage, V₂₂,of the capacitor C₂₂ reaches 4/8 V_(nom) and the voltage, V₁₁, of thecapacitor C₁₁ reaches 5/8 V_(nom) and the bus voltage, V_(bus), againreaches 9/8 V_(nom).

Next, the switch S₂ is turned off, the switch S₂₃ is turned on and thecapacitor C₂₃ is charged. This process is repeated until the capacitorC₂₄ is charged. At this point, the capacitor voltages V₁₁, V₁₂, V₂₁,V₂₂, V₂₃, and V₂₄, are 7/8 V_(nom); 3/8 V_(nom); 5/8 V_(nom); 4/8V_(nom); 3/8 V_(nom); and 2/8 V_(nom), respectively. The bus voltage,V_(bus), is 9/8 V_(nom).

Next, the capacitor C₁₁ is charged directly through the switches S_(h3),S_(h4), S₁₁ (with all other switches S_(h1), S_(h1), S₁₂, S₂₁, S₂₂, S₂₃,S₂₄ off) until the voltage, V₁₁, and the bus voltage, V_(bus), reach 9/8V_(nom). Now, the switch S_(h4) is turned off, and the switch S_(h2) isturned on along with the switch S_(h3). Hence, the bus voltage, V_(bus),again drops to 7/8 V_(nom).

Now, the capacitor C₁₁ can continue to charge up through the nownegatively connected capacitors C₂₁, C₂₂, C₂₃, C₂₄ through a processsimilar to the one described above, except that the capacitors C₂₁, C₂₂,C₂₃, C₂₄ are discharged in reverse order, i.e., first through C₂₄, thenthrough C₂₃, and so on until finally through C₂₁.

At this instant, the capacitor C₁₁ is fully charged to 13/8 V_(nom) andcharging of the capacitor C₁₂ must begin. For this, the H-bridgeswitches are toggled (i.e., the switches S_(h2) and S_(h3) are turnedoff, and the switches S_(h1) and S_(h4) are turned on), the switch S₁₁is turned off and the switch S₁₂ is turned on. The charging process forthe capacitor C₁₂ is identical to the charging process for the capacitorC₁₁. The switch states, the capacitor voltages (as seen from a portoutside the H-bridge, e.g. terminals 312 and 313 between sub-circuit 302and sub-circuit 304) and the resulting bus voltages, V_(bus), over acomplete charge and discharge cycle are shown in FIG. 5.

During the discharge period, the capacitors C₁₁, C₁₂ are discharged oneat a time through a process that is the reverse of the charging process.Hence, the voltage waveforms during the discharge period are a mirror ofthose in the charging period. Throughout the charging and dischargingperiod of the circuit 300, the bus voltage, V_(bus), stays within the7/8 V_(nom) to 9/8 V_(nom) range. Hence, the circuit 300 has a (nominalto peak) voltage ripple of 12.5%.

It is meaningful to compare various energy buffering circuits in termsof their energy buffering ratio, γ_(b). An energy buffering ratio,γ_(b), is a measure of how effectively a circuit makes use of the totalenergy storage capacity of its capacitors, E_(rated). It is defined asthe ratio of the energy that can be extracted in one cycle to E_(rated).If an energy buffering architecture can be charged up to a maximumenergy of E_(max) and drained down to a minimum energy of E_(min), thenthe energy buffering ratio, γ_(b), is given by:

γ_(b)=(E _(max) −E _(min))/(E _(rated))

The exemplary circuit 300 achieves an energy buffering ratio, γ_(b) of81.6%.

Referring to FIG. 6, another example of the SSC energy buffer 100 is acircuit 400 called a 1-3 unipolar SSC energy buffer circuit. The circuit400 includes a first set of circuitry 402 and a second set of circuitry404. The first set of circuitry 402 includes switches S₂₁, S₂₂, S₂₃connected in series to capacitors C₂₁, C₂₂, C₂₃, respectively, and these“legs” (switches in series with capacitors) are connected in parallel.The first set of circuitry 402 also includes a switch S₁₁ coupled inparallel to the capacitor switch pairs C₂₁-S₂₁, C₂₂-S₂₂ and C₂₃-S₂₃. Thesecond set of circuitry 404 includes a capacitor C₁₁.

The capacitors C₁₁, C₂₁, C₂₂, C₂₃ have corresponding voltages V₁₁, V₂₁,V₂₂, and V₂₃, respectively. The capacitors C₁₁, C₂₁, C₂₂, C₂₃ haveidentical capacitance, but different voltage ratings: 9/8 V_(nom) forC₁₁, 4/8 V_(nom) for C₂₁, 3/8 V_(nom) for C₂₂ and 2/8 V_(nom) for C₂₃,where V_(nom) is the nominal value of the bus voltage, V_(bus). Most ofthe energy is buffered by the capacitor C₁₁, which also supports most ofthe voltage, while the capacitors C₂₁, C₂₂ and C₂₃ play a supportivefunction, by buffering a small amount of energy and providing somevoltage support.

FIG. 7 depicts the voltage waveforms for the capacitors C₁₁, C₂₁, C₂₂,C₂₃ during a charging period for the circuit 400. Pre-charging circuitry(not shown in FIG. 6) ensures that each of capacitors C₁₁, C₂₁, C₂₂, C₂₃are charged to respective ones of the following initial voltages V₁₁,V₂₁, V₂₂ and V₂₃ In one embodiment, the initial voltages V₁₁, V₂₁, V₂₂,V₂₃ correspond to voltages of 4/8 V_(nom); 3/8 V_(nom); 2/8 V_(nom); and1/8 V_(nom). Once the circuit 400 starts to charge, the switch S₂₁ isturned on and the other switches S₂₂, S₂₃ and S₁₁ are turned off. Inthis case, the capacitors C₁₁, C₂₁ are placed in series with each otherand charged until the bus voltage, V_(bus), reaches 9/8 V_(nom), whenthe voltage, V₂₁, reaches 4/8 V_(nom), and the voltage, V₁₁, reaches 5/8V_(nom). Then, the switch S₂₁ is turned off, the switch S₂₂ is turnedon. After a next period of time (which may be the same as or similar tothe period of time taken to charge caps C₁₁, C₂₁ assuming a constantcharging current), the voltage, V₂₂, reaches 3/8 V_(nom) and thevoltage, V₁₁ reaches 6/8 V_(nom). Then, the switch S₂₃ is turned on andthe capacitor C₂₃ is charged. In this way, switches S₂₁, S₂₂, S₂₃, S₁₁are turned on and off one after another and the voltages V₂₁, V₂₂, V₂₃,V₁₁ finally reach the voltage values 4/8 V_(nom), 3/8 V_(nom), 2/8V_(nom) and 9/8 V_(nom), respectively. Then, the circuit 400 enters thedischarging period. The switches are turned on and off in reverse orderin the discharge cycle. Hence, the voltage waveforms during thedischarging period are the reverse of those in the charging period (notshown in FIG. 7).

Thus, by changing the switch configurations appropriately as energy isdelivered to and from the buffer port, individual capacitors can becharged/discharged over a wide range (from their initial voltages torated voltages), while the voltage at the buffer port, V_(bus), ismaintained within a narrow range (within ±12.5% of V_(nom)) as shown inFIG. 7. It can be shown that this simple structure can provide energybuffering of up to 8/11 (˜72.7%) of the peak energy storage rating ofthe capacitors, while providing a buffer port voltage, V_(bus), thatremains within ±12.5% of a nominal bus voltage, V_(nom).

Referring to FIG. 8, the circuit 400 can also be operated in slightlydifferent manner. For example, unlike the control strategy depicted inFIG. 7, a different control strategy gives equal time to all four switchstates. The required voltage rating of the capacitors C₂₁, C₂₂, C₂₃ islower than in FIG. 7. However, with this modification the energybuffering ratio of the buffer reduces to 68.4% compared to 72.7%depicted in FIG. 7.

Referring to FIG. 9, the circuit 400 can be extended to achieve asmaller bus voltage, V_(bus), variation or a higher energy bufferingratio, γ_(b), by adding more capacitors in parallel to the three uppercapacitors, C₂₁, C₂₂, C₂₃, shown in the circuit 400 (FIG. 6). Forexample, a circuit 400′ called a 1-m unipolar SSC energy buffer circuitincludes a first set of circuitry 402′ and the second set of circuitry404 which includes the capacitor C₁₁ similar to the circuit 400.However, the first set of circuitry 402′ includes additional switchesand capacitors than the first set of circuitry 402 in the circuit 400.For example, the first set of circuitry 402′ includes m “legs” inparallel (each “leg” consisting of a switch in series with a capacitor),m switches in series with the m capacitors and the switch S₁₁ inparallel with the m “legs”. Each of the m capacitors have equalcapacitance. The energy buffering ratio for the circuit 400′ is givenby:

$\gamma_{b} = \frac{{\left\lbrack {\left( {1 + R_{v}} \right)^{2} - \left( {1 - {mR}_{V}} \right)^{2}} \right\rbrack C_{1}} + \left( {mR}_{v} \right)^{2}}{{C_{1}\left( {1 + R_{v}} \right)}^{2} + {{C_{2}\left( {1 + 2^{2} + \ldots + m^{2}} \right)}R_{v}^{2}}}$

where R_(v) is the voltage ripple ratio (=0.5 (V_(max)−V_(min))/V_(nom),C₁ is the capacitance of the capacitor C₁₁ and C₂ is the capacitance ofone of the m capacitors each (which have equal capacitance).

Referring to FIG. 10, another type of SSC energy buffer circuit is acircuit 500 called a 1-3 bipolar SSC energy buffer circuit. Filmcapacitors are bipolar and can be charged in either direction. Thecircuit 500 takes advantage of this fact and thus improves the topologyand operating strategy in order to push the energy buffering ratio,γ_(b), even higher.

The circuit 500 includes a first set of circuitry 502 and a second setof circuitry 504. The first set of circuitry 502 includes 3 “legs” inparallel and switches S₂₁, S₂₂ and S₂₃ in series with a respective onecapacitor C₂₁, C₂₂, C₂₃, each set forming one leg. The first set ofcircuitry 502 also includes switches S_(h1), S_(h2), S_(h3), S_(h4)(e.g., an H-bridge). The second set of circuitry 504 includes acapacitor, C₁₁. The capacitors C₁₁, C₂₁, C₂₂, C₂₃ have identicalcapacitance values. The voltage ratings for the capacitors C₁₁, C₂₁,C₂₂, C₂₃ are 11/8 V_(nom), 3/8 V_(nom), 2/8 V_(nom) and 1/8 V_(nom), andrespectively. The main difference of this topology compared to unipolarone is that the four supporting capacitors are now put into the H-bridgeto enable bi-directional charging. For operating strategy, pre-chargingcircuitry (not shown) ensures that specified initial voltages are placedon the capacitors C₁₁, C₂₁, C₂₂, C₂₃ are 5/8 V_(nom), 2/8 V_(nom), 1/8V_(nom), 0 respectively. At first, switches S_(h1) and S_(h4) are turnedon and switches S_(h2) and S_(h3) are turned off. Then the circuit 500operates as a unipolar buffer as described above until the voltage ofthe four capacitors C₁₁, C₂₁, C₂₂, C₂₃ reaches 3/8 V_(nom), 2/8 V_(nom),1/8 V_(nom), and V_(nom), respectively. At this time, the switchesS_(h1) and S_(h4) are turned off and the switches S_(h2) and S_(h3) areturned on, thus the voltages of the capacitors C₂₁, C₂₂, C₂₃ seen fromthe outside are reversed to −3/8 V_(nom), −2/8 V_(nom) and −1/8 V_(nom),while the voltage of the capacitor, C₁₁, stays the same. After a similarprocess, the capacitors C₂₁, C₂₂, C₂₃ are charged back to −2/8 V_(nom),−1/8 V_(nom) and 0, respectively with the voltage of C₁₁ charged up to11/8 V_(nom).

After this, the discharging process begins and the capacitors C₂₁, C₂₂,C₂₃ are discharged down, flipped to a positive position and thendischarged again while C₁₁ is all the way discharged back to 5/8V_(nom).

Referring to FIG. 11, the waveforms of the voltage of each capacitorduring a charging period are shown. As described above, by changing theswitch configurations appropriately as energy is delivered to and fromthe buffer port, the individual capacitors can charge over a wide range(from their initial voltages to rated voltages), while the voltage atthe buffer port is maintained within a narrow range (within 12.5% ofV_(nom)). It can be shown that circuit 500 provides energy buffering of71.1% of the peak energy storage rating of the capacitors, whileproviding a buffer port voltage, V_(bus), that remains within ±12.5% ofa nominal bus voltage, V_(nom). While the energy buffering ratio, γ_(b),of the circuit 500 is lower than that of the circuit 400 (i.e., 1-3unipolar SSC energy buffer), the bipolar SSC energy buffer circuit witha slightly modified control and design methodology (as described furtherherein) increases its energy buffering ratio, γ_(b), to 74%.

Referring to FIG. 12, the circuit 500 can be extended by adding morecapacitors to the first and second of circuitry, 502, 504 as in acircuit 500′ called a n-m bipolar SSC energy buffer circuit. Note thatthe capacitor that does the energy buffering in the circuit 500 is thecapacitor C₁₁ in the second set of circuitry 504. Therefore, byreplacing C11 alone with a plurality of “legs” in parallel, each “leg”comprising the series connection of a capacitor and switch, betterbuffering performance can be achieved.

The circuit 500′ includes a first set of circuitry 502′ and a second setof circuitry 504′. The first set of circuitry 502′ includes capacitorsC₂₁, C₂₂, . . . , C_(2m) (referred herein as m capacitors) and switchesS₂₁, S₂₂, . . . , S_(2m) in series with a respective one capacitor, andthe “legs” formed by each switch-capacitor pair in parallel. The firstset of circuitry 502′ also includes switches S_(h1), S_(h2), S_(h3),S_(h4) (e.g., an H-bridge). The second set of circuitry 504 includescapacitors C₁₁, C₁₂, . . . , C_(1n) (referred herein as n capacitors)and switches S₁₁, S₁₂, . . . , S_(1n) in series with a respective onecapacitor, and the “legs” formed by each switch-capacitor pair inparallel.

The m capacitors in the first set of circuitry 502 in this case have toswitch at a higher switching frequency. The energy buffering ratio forthis n-m bipolar SSC energy buffer (with n capacitors of equal value C₁and m capacitors with equal value C₂) is given by:

$\gamma_{b} = \frac{{nC}_{1}\left\lbrack {\left( {1 + {2{mR}_{v}\frac{C_{2}}{C_{1} + C_{2}}}} \right)^{2} - \left( {1 - {2{mR}_{v}\frac{C_{2}}{C_{1} + C_{2}}}} \right)^{2}} \right\rbrack}{\left. {{nC}_{1}\left\lbrack {\left( {1 + {2{mR}_{v}\frac{C_{2}}{C_{1} + C_{2}}}} \right)^{2} - {{C_{2}\left( {1 + 2^{2} + \ldots + m^{2}} \right)}R_{v}^{2}}} \right)} \right\rbrack}$

Referring to FIG. 13, the variation in energy buffering ratio, γ_(b), asa function of the number of n capacitors and number of m capacitors isshown. FIG. 13 indicates that there is an optimal number of m capacitorsthat should be used for a given number of n capacitors in order tomaximize the energy buffering ratio, γ_(b). Note that this optimalnumber of m capacitors depends on the value of allowed voltage rippleratio, R_(v). In FIG. 13, the voltage ripple ratio, R_(v), is 12.5%.

FIGS. 14A and 14B show how the optimal number of m capacitors changes asthe allowed voltage ripple ratio, R_(v), is changed. FIG. 14A has avoltage ripple ration, R_(v), of 25%. FIG. 14A has a voltage rippleratio, R_(v), of 6.25%. If a larger voltage ripple ratio, R_(v), isallowed a higher energy buffering ratio, γ_(b), can be achieved withfewer m capacitors. On the other hand, a lower voltage ripple, R_(v),requires a larger number of m capacitors if maximum energy buffering isto be achieved. However, increasing the number of m capacitors alsoincreases the complexity of the circuit. Therefore the number of mcapacitors to use can be determined by an appropriate trade-off betweenvoltage variation and energy buffering ratio, γ_(b).

Referring now to FIG. 15, one particular example of the circuit 500′ isa circuit 500′ where n=2 and m=6 also called a 2-6 bipolar stackedswitched capacitor energy buffer circuit.

Exemplary circuit 500′ includes a first block of parallel coupledswitches and capacitors S11, C11, S12, C12 and a second block ofparallel coupled switches and capacitors S21, C21, S22, C22, S23, C23,S24, C24, S25, C25, S26, C26. The first and second blocks are coupled inseries across a bus voltage V_(bus). Switches Sh1, Sh2, Sh3, Sh4 aredisposed in the second block to provide selected signal paths betweenthe first and second blocks.

As noted above, the capacitors are preferably of a type that can beefficiently charged and discharged over a wide voltage range (e.g., filmcapacitors). The switches are disposed to selectively couple thecapacitors to enable dynamic reconfiguration of both the interconnectionamong the capacitors and their connection to a buffer port. The switchesare cooperatively operated as a switching network such that the voltageseen at the buffer port varies only over a small range as the capacitorscharge and discharge over a wide range to buffer energy.

By appropriately modifying switch states of the SSC energy buffercircuit, the SSC energy buffer circuit absorbs and delivers energy overa wide individual voltage range, while maintaining a narrow-rangevoltage at the input port. This enables maximal utilization of theenergy storage capability.

The waveforms associated with the circuit 500″ are shown in FIG. 16.

Referring now to FIG. 16, a plot of switching states vs. voltage isshown for the circuit 500″ (FIG. 15).

The bipolar stacked switched capacitor energy buffer circuit (e.g., thecircuit 500′) previously described can also be controlled in a slightlydifferent manner. Instead of charging the n capacitors only in serieswith the m capacitors, a state can be introduced by turning S_(h3) andS_(h4) (or S_(h1) and S_(h2)) on at the same time in which the ncapacitor is charged directly. An example of the modified control isshown in FIG. 5 for the circuit 300 (the 2-4 bipolar SSC energy buffercircuit) of FIG. 4. The modified control is described herein in thesection entitled: “Enhanced Bipolar Stacked Switched Capacitor EnergyBuffer”]. With this modified control, and assuming that all m and ncapacitors have the same capacitance, the expression for energybuffering ratio, γ_(b) becomes:

$\gamma_{b} = \frac{n\left\lbrack {\left( {1 + {\left( {m + 1} \right)R_{v}}} \right)^{2} - \left( {1 - {\left( {m + 1} \right)R_{v}}} \right)^{2}} \right\rbrack}{\left. {n\left\lbrack {\left( {1 + {\left( {m + 1} \right)R_{v}}} \right)^{2} - {\left( {2^{2} + 3^{3} + \ldots + \left( {m + 1} \right)^{2}} \right)R_{v}^{2}}} \right)} \right\rbrack}$

This is plotted as a function of number of n capacitors and number of mcapacitors in FIG. 17. FIG. 17 also plots (as dashed lines) the energybuffering ratio without modified control. The modified control achieveshigher maximum energy buffering ratio than without the modified control.Furthermore, it achieves this higher maximum with fewer m capacitorsthan without modified control.

The techniques described herein are not limited to the specificembodiments described. Elements of different embodiments describedherein may be combined to form other embodiments not specifically setforth above. Other embodiments not specifically described herein arealso within the scope of the following claims.

What is claimed is:
 1. A stacked switched capacitor (SSC) energy buffercircuit comprising: two sub-circuits that are serially coupled during afirst operating mode wherein each sub-circuit comprises one or morecapacitors, and at least one sub-circuit further comprises a pluralityof switches disposed to selectively couple the capacitors to: (a) enabledynamic reconfiguration of how the capacitors are coupled to theterminals of the sub-circuit; and (b) dynamically reconfigure theinterconnection among the capacitors within the sub-circuit.
 2. The SSCenergy buffer circuit of claim 1 wherein the switches in at least one ofthe two sub-circuits are arranged to dynamically reconfigure a polaritywith which at least one capacitor is connected to the terminals of thesub-circuit.
 3. The SSC energy buffer circuit of claim 1, furthercomprising a pre-charge circuit coupled to each of the two sub-circuitssaid pre-charge circuit operable to charge each of the one or morecapacitors in the two sub-circuits to specified initial conditionsbefore entering the first operating mode.
 4. The SSC energy buffercircuit of claim 1 wherein at least one subcircuit comprises a pluralityof sub-sub-circuits connected in parallel, wherein each sub-sub-circuitcomprises a switch serially coupled to a capacitor.
 5. The SSC energybuffer circuit of claim 1 wherein the peak energy buffered one of thetwo sub-circuits is greater than 66% of the total peak energy bufferingcapability.
 6. The SSC energy buffer circuit of claim 1 wherein thecapacitors in at least one of the two sub-circuits are of a type thatcan be efficiently charged and discharged over a wide voltage range. 7.The SSC energy buffer circuit of claim 1 wherein the capacitors in atleast one of the first and second blocks are provided as: one of filmcapacitors, ultra capacitors and electrolytic capacitors.
 8. The SSCenergy buffer circuit of claim 1 wherein the switches are disposed toselectively couple the capacitors to enable dynamic reconfiguration ofboth the interconnection among the capacitors and their connection to abuffer port.
 9. The SSC energy buffer circuit of claim 1 wherein theswitches are cooperatively operated as a switching network such that thevoltage seen at a buffer port varies only over a small range as thecapacitors charge and discharge over a wide voltage range to bufferenergy.
 10. A circuit comprising: a first set of circuitry comprising: mcapacitors; and m switches, each m switch serially coupled to acorresponding one of the m capacitors; and a second set of circuitrycomprising: n capacitors; and n switches, each n switch serially coupledto a corresponding one of the n capacitors; wherein a voltage across thefirst set of circuitry and the second set of circuitry is a bus voltage,wherein the circuit is configured to maintain the bus voltage within apredetermined range of a nominal value, and wherein n and m are integersgreater than zero.
 11. The circuit of claim 10 wherein the first set ofcircuitry includes an H-bridge switch and wherein said H-bridge switchis disposed to allow at least some of said m capacitors to be charged ina bipolar fashion.
 12. The circuit of claim 10 wherein n=2 and m=4, andwherein the circuit has an energy buffering ratio, γ_(b) of 81.6%. 13.The circuit of claim 10 wherein n=1 and m=3, and wherein the circuit hasan energy buffering ratio of:${\gamma_{b} = \frac{{nC}_{1}\left\lbrack {\left( {1 + {2{mR}_{v}\frac{C_{2}}{C_{1} + C_{2}}}} \right)^{2} - \left( {1 - {2{mR}_{v}\frac{C_{2}}{C_{1} + C_{2}}}} \right)^{2}} \right\rbrack}{\left. {{nC}_{1}\left\lbrack {\left( {1 + {2{mR}_{v}\frac{C_{2}}{C_{1} + C_{2}}}} \right)^{2} - {{C_{2}\left( {1 + 2^{2} + \ldots + m^{2}} \right)}R_{v}^{2}}} \right)} \right\rbrack}},$where R_(v) is the voltage ripple ratio, C₁ is the capacitance of the ncapacitor and C₂ is the capacitance of one of the m capacitors which areequal in capacitance.
 14. The circuit of claim 10 wherein the circuithas an energy buffering ratio of:$\gamma_{b} = \frac{n\left\lbrack {\left( {1 + {\left( {m + 1} \right)R_{v}}} \right)^{2} - \left( {1 - {\left( {m + 1} \right)R_{v}}} \right)^{2}} \right\rbrack}{\left. {n\left\lbrack {\left( {1 + {\left( {m + 1} \right)R_{v}}} \right)^{2} - {\left( {2^{2} + 3^{3} + \ldots + \left( {m + 1} \right)^{2}} \right)R_{v}^{2}}} \right)} \right\rbrack}$where R_(v) is the voltage ripple ratio, C₁ the capacitance of the n andm capacitors are equal.
 15. The circuit of claim 10 wherein the m and ncapacitors are film capacitors.
 16. The circuit of claim 10 wherein them capacitors have the same capacitance.
 17. The circuit of claim 10wherein the n capacitors have the same capacitance.
 18. The circuit ofclaim 10 wherein the m and n capacitors have the same capacitance. 19.The circuit of claim 10, further comprising a switch coupled to said mcapacitors, and wherein m=3 and n=1, and wherein the circuit has anenergy buffering ratio, γ_(b) of about 72.7%.
 20. The circuit of claim10 wherein n=1, and wherein an energy buffering ratio is equal to:$\gamma_{b} = \frac{{\left\lbrack {\left( {1 + R_{v}} \right)^{2} - \left( {1 - {mR}_{V}} \right)^{2}} \right\rbrack C_{1}} + \left( {mR}_{v} \right)^{2}}{{C_{1}\left( {1 + R_{v}} \right)}^{2} + {{C_{2}\left( {1 + 2^{2} + \ldots + m^{2}} \right)}R_{v}^{2}}}$where R_(v) is the voltage ripple ratio, C₁ is the capacitance of the ncapacitor and C₂ is the capacitance of one of the m capacitors which areequal in capacitance.
 21. A grid interface power converter systemcomprising: a stacked switched capacitor (SSC) energy buffer circuitcoupled between a DC-DC converter and an AC-DC converter, said stackedswitched capacitor (SSC) energy buffer circuit comprising: twosub-circuits that serially coupled during a first operating mode whereineach sub-circuit comprises one or more capacitors, and at least onesub-circuit further comprises a plurality of switches disposed toselectively couple the capacitors to: (a) enable dynamic reconfigurationof how the capacitors are coupled to the terminals of the subcircuit;and (b) dynamically reconfigure the interconnection among the capacitorswithin the subcircuit.
 22. The circuit of claim 21 said SSC energybuffer circuit comprises: a first set of circuitry comprising: mcapacitors; and m switches, each m switch serially coupled to acorresponding one of the m capacitors; and a second set of circuitrycomprising: n capacitors; and n switches, each n switch in series with acorresponding one of the n capacitors; wherein a voltage across thefirst set of circuitry and the second set of circuitry is a bus voltage.23. The circuit of claim 21 wherein the SSC energy buffer circuit isconfigured to maintain the bus voltage within ±12.5% of a nominal value.24. The SSC energy buffer circuit of claim 21 wherein the switches in atleast one of the two sub-circuits are arranged to dynamicallyreconfigure a polarity with which at least one capacitor is connected tothe terminals of the sub-circuit.
 25. The SSC energy buffer circuit ofclaim 21, further comprising a pre-charge circuit coupled to each of thetwo sub-circuits said pre-charge circuit operable to charge each of theone or more capacitors in the two sub-circuits to specified initialconditions before entering the first operating mode.
 26. The SSC energybuffer circuit of claim 21 wherein at least one subcircuit comprises aplurality of sub-sub-circuits connected in parallel, wherein eachsub-sub-circuit comprises a switch serially coupled to a capacitor. 27.The SSC energy buffer circuit of claim 21 wherein the peak energystorage capability of one of the two sub-circuits is greater than 66% ofthe total peak energy storage capability.
 28. A stacked switchedcapacitor (SSC) energy buffer circuit having first and second terminals,the SSC energy buffer circuit comprising: a first sub-circuit comprisingone or more capacitors; a second sub-circuit comprising one or morecapacitors; and one or more switches disposed in at least one of saidfirst and second sub-circuits to selectively couple said one or morecapacitors and wherein said first and second sub-circuits are seriallycoupled during a first operating mode and wherein said one or moreswitches are operable to enable dynamic reconfiguration of how thecapacitors are coupled to the terminals of the sub-circuit;
 29. The SSCenergy buffer circuit of claim 28 wherein said one or more switches areoperable to dynamically reconfigure the interconnection among thecapacitors within at least one of said first and second sub-circuits.30. The SSC energy buffer circuit of claim 29 wherein in at least someoperating modes, said one or more switches are operable to prevent thecapacitors from ever being connected together at both terminals.